FinFETs to enable new generations of high-density, high-performance, ultra-low-power SoCs

Cadence this year is nominating the FinFET, a new type of 3D transistor that promises significant power and performance advantages over the planar devices that are in common use today. FinFETs are now expected to come into common use at process nodes below 20nm, where they will allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs will thus enable new generations of high-density, high-performance and ultra-low-power systems on chip (SoCs) for future smart phones, tablets and other advanced mobile devices.

FinFET technology was co-invented and described in 1999 by Chenming Hu, Tsu-Jae King-Liu, and Jeffrey Bokar at the University of California, Berkeley. Their research was a response to a request for proposal from the DARPA (Defense Advanced Research Projects Agency) for ideas on how to create ICs at 25nm and below.

In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor's elevated channel or "fin". This solves several problems, including random variation of impurity atoms and variations in gate length. This approach also provides much more control over electrical current compared to planar or flat transistors. As a result, FinFETs both improve performance and reduce power consumption. Furthermore, they were proven to be commercially manufacturable in the spring of 2011 by Intel at 22nm, and most recently by IBM working with ARM and Cadence at 14nm.

Because the FinFET channel is surrounded on three sides by the gate, and gates turn on and off much faster than with planar transistors, leakage is substantially reduced. Vdd and dynamic power are significantly lower as well. Designers can add multiple fins to provide more current. While the last several generations of technology nodes used 1 volt power supplies, FinFET technology could allow designers to go to 0.8V or 0.6V, which helps to reduce dynamic power.

An important feature of FinFET technology is the fin thickness, which needs to be smaller than or equal to the gate length. Transistor scaling is not limited by oxide thickness. This is good aspect of the technology because current process lithography defines the FET characteristics at each new process node. It only takes one extra mask to create the silicon fin, which helps manage costs. The FinFET manufacturing process is also compatible with contemporary advanced CMOS manufacturing and production techniques. After the fin is constructed, the rest of the processing is essentially planar because the fin height is only about 30nm for a fin that's 20nm thick.
 

 

Like any new semiconductor technology, FinFETs will rely on an ecosystem that includes EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes. Early collaboration and R&D investment by EDA vendors, IP providers, foundries, and semiconductor companies is crucial. In the coming year Cadence will continue actively working with its partners on EDA support, SPICE models, and test chips for next generation SoCs at 14nm and beyond.

- Chi-Ping Hsu, Senior Vice President, Research and Development, Silicon Realization, Cadence Design Systems, Inc.