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Nickname: Clive Maxfield     Articles(320)     Visits(232736)     Comments(61)     Votes(212)     RSS
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Posted: 06:43:20 PM, 03/04/2014

Altera, Intel to partner on multi-die 14nm FPGAs

   

Well, as usual, things are racing along in the programmable logic space (where no one can hear you scream). Around the middle of 2013, Altera detailed its roadmap for the 20 nm and 14 nm technology nodes.


Arria 10 FPGAs and SoCs will be implemented using TSMC's 20 nm process, while Stratix 10 FPGAs and SoCs are to leverage Intel's 14 nm Tri-Gate process.


Of course, nothing happens in isolation. Just a few weeks ago, as I pen these words, Zvi Or-Bach from MonolithIC 2D Inc. published a column saying that he believes 28 nm is actually the last node of Moore's Law. As Zvi says: "Beyond this point, we can continue to make smaller transistors and pack more of them into the same size die, but we cannot continue to reduce the cost. In most cases, in fact, the same SoC will actually have a higher cost!"


Well, that doesn't sound too good, does it? On the bright side, however, instead of creating everything on one humongous—and expensive—die implemented at the latest and greatest technology node, it is possible to combine an optimal mix of dies for an application, where each die may boast different functionality (FPGA fabric, DRAM, SRAM, analogue, etc.) and where each die may potentially be realised at a different technology node.


All of which brings us to Altera's announcement, which is that it and Intel have agreed to extend their manufacturing partnership to include the development of multi-die devices. (Click here to see the full press release.) This collaboration will include optimising the integration of Altera's Stratix 10 FPGAs and SoCs implemented using Intel's 14 nm FinFET technology with other heterogeneous technologies into a single system-in-package (SiP).

 


Personally I think is a really good approach. I am, of course, also excited by the thought of 3D FPGA/SoC implementations and of true monolithic IC technologies, but combining multiple heterogeneous dies into a single SiP has a lot of advantages in terms of cost and yield and getting something into my sweaty hands sooner rather than later. As always, it's going to be interesting to see how things develop over the course of the next year or two. Watch this space...


 

Label: intel fpga altera
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