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Building PCIe endpoint devices with FPGAs
Posted: May 23, 2008 1:47 AM

This article will review the factors for building single-chip x4- and x8-lane PCIe designs with the ...[ View complete article ]


Message: Building PCIe endpoint devices with FPGAs Post time: May 23, 2008 1:47 AM
 

Author: Tim.Fairfield

Level: Interns

Points: 115

This article will review the factors for building single-chip x4- and x8-lane PCIe designs with the latest FPGA technology.
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( 1 ) Reply:Building PCIe endpoint devices with FPGAs Post time: May 23, 2008 1:47 AM
 

Author: Tim.Fairfield

Level: Interns

Points: 115

I don't see any info on time to load the PCIe logic to the FPGA with the configuration loader and having it live before the Host system BIOS enumerates the device. If the PCIe decode logic isn't up and working before the BIOS hits it, the device will not be enumerated. This is a serious issue in non embedded design with any FPGA PCIe implementation.
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