In this position, you will be working as a member of the IC design team developing Hard IP on next generation deep submicron process for the microprocessors and System-On-Chip (SOC) ICs. You will be performing tasks related to VLSI CMOS IC design and physical layout including: circuit design of high speed or high voltage IO [USB2, DDR, HDMI, MIPI, eMMC, GPIO]. You will be performing timing, functional and reliability analysis and supervise physical layout designers. You will be providing support for full-chip pre-silicon and post-silicon validation, system validation, product test, quality and reliability to ensure the implementation of feature sets in the final product.
BSc, MSc or PhD in Electronics Engineering with at least 8 years' relevant experience. The candidate should have strong analytical and management skills, any relevant amount of experience in analog circuit design and management would be an added advantage.
Additional qualifications include:
-Strong background in high speed serial interfaces like PCIe2, USB2, MIPI, Serdes, HDMI.
-Background in high voltage interface in sub-micron process like DDR, GPIO and HDMI.
-Experience in SoC and HIP design methodology .
-Experience leading a highly technical team from development to product PRQ.