Description

In this position, you will be involved in the physical design & implementation of next generation Hard IP interfaces for various computing devices.

You will have the chance to work in a challenging, fluid and dynamic environment with a diverse team of engineers who are delivering customized and optimized digital design logic.

Your day to day activities typically involves close collaboration with engineers who are delivering technical solutions spanning most of the ASIC flow.

These activities include but are not limited to:
- Debugging, analyzing and root causing problems that will ideally result in a proposed solution that is then subjected to a verification process;
- Assisting the team in various tasks with the aim of gaining the relevant experience and familiarity with industry leading flows, processes and requirements;
- Improving and automating existing tasks and activities for greater efficiencies.

 
http://jobs.intel.com/mobile/job/Penang-Graduate-Trainee-Job/66428600/